As circuit density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. One additional technique finding greater application in achieving higher circuit density is to form field effect transistors with thin films, which are stacked and integrated on top of a substrate containing conventional field effect transistors. This is commonly referred to as "thin film transistor" (TFT) technology. These transistors are formed using thin layers which constitute all or a part of the resultant source and drain regions.
Specifically, typical prior art TFT's are formed from a thin film of semiconductive material (typically polysilicon). A central channel region of the thin film is masked by a separate layer, while opposing adjacent source/drain regions are formed with an appropriate p or n type conductivity enhancing impurity. A gate insulator and gate are provided either above or below the thin film channel region, thus providing a field effect transistor having active and channel regions formed within a thin film as opposed to a bulk substrate.
One common material utilized as the thin source, channel and drain film in a TFT is polysilicon. Such is comprised of multiple forms of individual single crystal silicon grains. The locations where two individual crystalline grains abut one another is commonly referred to as a grain boundary. Grain boundaries are inherent in polycrystauline materials, such as polysilicon. The crystalline structure breaks down at the grain boundaries, giving rise to a high concentration of broken or "dangling" Si bonds. These dangling bonds "trap" carriers and give rise to potential barriers at the grain boundaries. These potential barriers impede the flow of carriers in polysilicon, thus reducing conductivity. The grain boundary potential barrier height is proportional to the square of the dangling bond density, or "trap density". Therefore, the smaller the grain size, the higher the trap density and thus the lower the conductance. Conversely, a larger grain size results in a higher conductance.
In a TFT, the grain boundary potential barrier height is modulated by the gate voltage, and hence the conductivity is a function of the gate voltage, as opposed to a resistor, where the barrier height is not modulated. Also, in terms of transistor switching characteristics a larger trap concentration makes it harder for the gate to form a channel resulting in a higher threshold voltage and a lower drive current as compared to bulk transistors. The grain boundary trap concentration also affects the leakage current in TFTs. In polysilicon or other polycrystalline TFTs, the grain boundary traps at the drain end can dramatically increase the leakage current in the presence of a "gate-to-drain" electric field. The increase in leakage results from either "thermionic field emission" and/or "Poole-Frenkel" emission through the grain boundary traps. Accordingly, the greater the number of grain boundaries (i.e., the smaller the grain size), the greater the current leakage through the material. Greater current leakage means that more power is required to replace the leaking current to maintain an SRAM cell transistor or a pixel in a flat panel display in its desired state. Such leakage is particularly adverse in laptop computers, where desired power consumption when a cell's state is not being changed would be desired to be very low to extend battery life.
Therefore, it would be desirable to provide a thin film field effect transistor which is operable to obtain the individual benefits to be derived from related prior art manufacturing processes and practices while avoiding the detriments individually associated therewith.